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TDA9951
CEC/I2C-bus translator
Rev. 01 -- 7 August 2008 Product data sheet
1. General description
The TDA9951 is a single-chip Consumer Electronics Control (CEC) to I2C-bus translator dedicated to the control and interfacing Consumer Electronics products. The built-in processor simplifies Consumer Electronics (CE) product CPU design by managing a range of interfacing and control functions including the CEC protocol, timings and interrupts. Designed as an I2C-bus slave device the TDA9951 enables control of these features to any I2C-bus master device such as the CE host processor. This data sheet describes the I2C-bus interface, together with the control and management features of the TDA9951. The TDA9951 is an enhancement of the TDA9950.
2. Features
I CEC support: N Receive and transmit messages using compliant signal free time handling N Up to 16 bytes message length N Multiple logical addresses N Comprehensive arbitration and collision handling I Dedicated processor control of CEC-line and I2C-bus interface utilizing embedded software I I2C-bus interface to host communication in Standard mode (100 kbit/s) and Fast mode (400 kbit/s) I Automatic Idle mode reduces power consumption if no messages are on CEC-line and I2C-bus plus I Managed Standby and Wake-up power modes I Active LOW reset input and on-chip Power-On Reset (POR) enables operation without external reset components I Reset counter and reset glitch circuitry prevents false and incomplete resets I Programmable on-chip retry counter I Controls specific Vacuum Fluorescent Display (VFD) devices and/or up to four LEDs I Decode up to 10 panel switches I Decode infrared protocol RC5, RC5 enlarged and RC6 Mode 0 I Battery operation detection maintains clock and calendar in low power mode I Provides real-time clock features including time-of-day alarm and periodic timer I VDD operating range 3.0 V to 3.6 V I 5 V tolerant input/output pins I On-chip oscillator for a 12 MHz crystal I Schmitt trigger port inputs
NXP Semiconductors
TDA9951
CEC/I2C-bus translator
3. Applications
I I I I I I I All devices using an HDMI connector YCbCr or RGB high-speed video digitizer Projector, plasma and LCD TV Rear-projection TV High-end TV Home-theater amplifier DVD recorder
4. Quick reference data
Table 1. Symbol VDD Tamb Ptot Quick reference data Parameter supply voltage ambient temperature total power dissipation based on package heat transfer, not device power consumption Standard mode Fast mode Conditions Min 2.4 -40 Typ 3.0 Max Unit 3.6 +85 1.5 V C W
I2C-bus: pins SDA and SCL; 5 V tolerant fclk clock frequency 100 400 kHz kHz
5. Ordering information
Table 2. Ordering information Package Name TDA9951TT TSSOP28 Description plastic thin shrink small outline package; 28 leads; body width 4.4 mm Version SOT361-1 Type number
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TDA9951
CEC/I2C-bus translator
6. Block diagram
VFD_CLK VFD_DAT VFD_STR VFD_BLK CEC_OUT CEC_IN
VFD INTERFACE
TX BUF1 RX BUF2 RX BUF3 SDA I2C-BUS INTERFACE RX BUF4 RX BUF5
CEC INTERFACE
REALTIME CLOCK INTERFACE
SCL
INT
KEY SCAN INTERFACE
KROWn(1) KCOL
A0
IR INTERFACE
IR_DAT IR_VAL
MANAGEMENT WATCHDOG
STANDBY INTERFACE
SBY PSEN
001aai275
(1) Where n is 0, 1, 2, 3 and 4.
Fig 1.
Block diagram
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TDA9951
CEC/I2C-bus translator
7. Pinning information
7.1 Pinning
VFD_CLK VFD_DAT SBY INT CEC_OUT RST_N VSS XTAL1 XTAL2
1 2 3 4 5 6 7 8 9
28 IR_DAT 27 IR_VAL 26 A0 25 RSVD2 24 KROW0 23 KROW1 22 KROW2 21 VDD 20 KROW3 19 KROW4 18 RSVD1 17 RSVD0 16 PSEN 15 KCOL
001aai276
TDA9951
CEC_IN 10 SDA 11 SCL 12 VFD_STR 13 VFD_BLK 14
Fig 2.
Pin configuration
7.2 Pin description
Table 3. Symbol VFD_CLK VFD_DAT SBY Pin description Pin 1 2 3 Type[1] O O O Description pulsed HIGH to clock output of the VFD display driver data output to the VFD display driver power control output to the host processor. Operating mode = LOW-level Standby mode = HIGH-level INT 4 O interrupt line to the host processor. Indicates data is available for reading. The polarity of operation is configured using the common configuration register; default is INT_POL bit = 1, active-HIGH output to the CEC interface[2] external reset input. Holding this input LOW resets the TDA9951. It must be held LOW for a time after power-up when using an 18 MHz crystal[2]. ground; 0 V reference input to the oscillator and internal clock generator circuits (18 MHz crystal)[2] output from the oscillator amplifier input from the CEC interface[2] I2C-bus serial data input/output[2] I2C-bus serial clock input[2]
CEC_OUT RST_N
5 6
O I
VSS XTAL1 XTAL2 CEC_IN SDA SCL
7 8 9 10 11 12
GND I O I I/O I
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TDA9951
CEC/I2C-bus translator
Pin description ...continued Pin 13 14 15 16 Type[1] O O O I Description VFD strobe line. Pulsed HIGH latches clocked output at the VFD driver VFD blank line. Default HIGH blanks output at the VFD display driver. The polarity is configurable using the I2C-bus key matrix column output[2] power sense input detects power supply type. LOW-level = battery HIGH-level = main power
Table 3. Symbol VFD_STR VFD_BLK KCOL PSEN
RSVD0 RSVD1 KROW4 KROW3 VDD KROW2 KROW1 KROW0 RSVD2 A0
17 18 19 20 21 22 23 24 25 26
I O I I P I I I O I
reserved pin; connect to ground reserved pin key matrix row input[2] key matrix row input[2] power supply voltage key matrix row input[2] key matrix row input[2] key matrix row input[2] reserved pin I2C-bus slave address bit. This pin configures the least significant bit A0 of the I2C-bus slave address; connect to: VDD (HIGH) sets A0 to logic 1 (address 35h) VSS (LOW) sets A0 to logic 0 (address 34h)
IR_VAL IR_DAT
27 28
O I
pulse LOW for 65 ms after every valid IR frame is received, to indicate activity using an LED input from external infrared demodulator. LOW-level = active IR pulse, HIGH-level = no IR pulse (a space)
[1] [2]
P = power supply, I = input, O = output and I/O = Input and Output. See Figure 15 "Application diagram" on page 35.
8. Functional description
The TDA9951 controls the interface between the CEC-line and the I2C-bus using its internal processor and embedded software.
8.1 Device addressing
The SDA and SCL pins are managed by the I2C-bus peripheral which automatically communicates in Standard mode (100 kbit/s) or Fast mode (400 kbit/s) as an I2C-bus slave. The TDA9951 signals the host processor that data is ready by asserting the INT output. The polarity is configurable using the INT_POL bit in the CCONR register (see Table 14).
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TDA9951
CEC/I2C-bus translator
The seven-bit I2C-bus slave address is hard-coded as 34h and can be changed to 35h by setting the pin A0, as shown in Table 3 and Table 4. This enables two TDA9951 to be connected to the same host using the addresses 34h and 35h. Alternatively, changing the address enables one TDA9951 to avoid address clashes with other I2C-bus slaves.
Table 4. Bit Value I2C-bus slave address 7 0 6 1 5 1 4 0 3 1 2 0 1 A0 0 R/W
8.2 Configuring the TDA9951
The TDA9951 is controlled using a series of registers.
Table 5. Register APR CSR CER CVR CCR ACKH ACKL CCONR CDR I2C Register configuration Description Address Pointer Register Common Status Register Common Error Register Common Version Register Common Control Register Address 00h 00h 01h 02h 03h Read/Write W R R R R/W R/W R/W R/W R/W Reference Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 14 Table 15
CEC Address ACK High register 04h CEC Address ACK Low register 05h Common Configuration Register 06h Common Data Registers 07h to 19h
The first byte of any I2C-bus write frame configures the address pointer register APR. This determines the TDA9951 register accessed by the next I2C-bus read or write. If for example, a read is carried out without first writing to the address pointer register, the register returned is the register that address pointer register was last set to. The address pointer auto-increments after each successful read or write for all address pointer values other than 00h. When the address pointer register is set 00h, the common status register is polled using successive reads without needing to reset the address pointer register each time. When the address pointer register is set higher than 07h, this is treated as setting it to 07h. This is because all message data transfers must start from register 07h and continue by auto-incrementing in one contiguous transfer. When the host writes to two or more non-contiguous registers, two separate write sequences are used with either a STOP/START sequence or repeated START between them. Before a read takes place, the host must first write to the address pointer register (if required) and then, repeat the START condition or STOP/START sequence. Finally, it starts reading data bytes until the read sequence is complete.
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TDA9951
CEC/I2C-bus translator
8.3 Using the INT line
The TDA9951 is an I2C-bus slave device and when data is ready to be read, it uses the INT output line to signal the host processor. The common configuration register INT_POL bit sets the operating polarity of the INT line. When the INT line is active, it matches the state of the INT_POL bit. The INT line state is updated in the common status register making it possible to poll the register instead of monitoring the INT line. This method is less efficient consequently, it is not recommended. The common status register INT indication is not affected by the common configuration register INT_POL bit.
8.4 Register descriptions
Table 6. Bit 7 to 5 4 to 0 APR - Address pointer register (address 00h) bit description Symbol reserved Access W Value 000 Description reserved address pointer: Address of the register to be read/written in the next I2C-bus communication.
REG_PTR[4:0] W
Table 7. Bit 7 6 5
CSR - Common status register (address 00h) bit description Symbol BUSY INT ERR Access R R R Value 0 1 0 1 0 1 Description default; requests accepted busy; cannot accept further requests default; INT interrupt output is inactive the INT interrupt output is active default; no error an error occurred; cleared on reading the common error register default; the SBY (standby) output pin is inactive LOW the SBY output pin is HIGH the PSEN input pin is LOW the PSEN input pin is HIGH not used (must be set to 000)
4
SBY
R
0 1
3 2 to 0 Table 8. Bit 7 to 0
PSEN
0 1 000
CER - Common error register (address 01h) bit description Symbol CER[7:0] Access R Value Description This register contains details of the last error. Reading this register resets the ERR bit in the common status register 00h 01h 02h 03h no error has occurred since reset a watchdog reset has occurred a long CEC message with no End Of Message (EOM) was detected CEC input has overrun. No buffer was available to hold new data
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TDA9951
CEC/I2C-bus translator
This register enables the host processor to read the TDA9951 software version.
Table 9. Bit 7 to 4 3 to 0 CVR - Common version register (address 02h) bit description Symbol CVR_MIN[3:0] Access R Value Description major version minor version CVR_MAJ[3:0] R
Table 10. Bit 7
CCR - Common control register (address 03h) bit description Access R/W W Value 0 1 Description no action resets the TDA9951 and returns it to its power-up state. CEC transmissions are completed before the reset. Only performed when the TDA9951 is in Idle mode, restores all default values. default; the CEC interface is disabled after completion or reception of a pending CEC transmission. Further messages on the CEC line and messages for transmission are no longer acknowledged or accepted. The CEC interface is enabled and acknowledges messages based on the contents of the CEC address ACK high and address ACK low registers. default; ignores RC5 commands from the IRX interface accepts RC5 commands default; ignores RC6 commands from the IRX interface accepts RC6 commands default; key matrix is disabled key matrix is enabled default; VFD display output is disabled VFD display output is enabled not used enters Standby mode and sets the SBY output. This bit is then cleared automatically. The common status register SBY bit indicates the SBY output state
Symbol RESET
6
CEC
R/W
0
1
5
RC5
R/W
0 1
4
RC6
R/W
0 1
3 2 1 0
KEY VFD not used SBY
R/W R/W R/W
0 1 0 1 0 1
Table 11. Bit 7 6 to 0
ACKH - CEC address ACK high register (address 04h) bit description Access R R/W 0 1 Value 0 Description reserved; must be set to 0 for each bit: messages are not acknowledged messages are acknowledged and forwarded to the host
Symbol reserved ACKH[6:0]
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CEC/I2C-bus translator
ACKL - CEC address ACK low register (address 05h) bit description Access R/W 0 1 Value Description for each bit: messages are not acknowledged messages are acknowledged and forwarded to the host
Table 12. Bit 7 to 0
Symbol reserved
Using ACKH and ACKL, each bit of ADDR[14:0] corresponds to a CEC logical address. CEC reserves ADDR[15] as a broadcast address. ADDR[14:0] is built-up from ACKH[6:0] and ACKL[7:0].
Table 13. Bit ACKH ADDR[14:0] definition 7 6 ADDR[6] 5 ADDR[5] 4 ADDR[4] 3 ADDR[3] 2 ADDR[2] 1 0 ADDR[14] ADDR[13] ADDR[12] ADDR[11] ADDR[10] ADDR[9] ADDR[8] ADDR[1] ADDR[0]
ACKL ADDR[7] Table 14. Bit 7 to 5 4
CCONR - Common configuration register (address 06h) bit description Access R R/W 0 Value 000 Description not used; set to 000 controls how the TDA9951 notifies the host processor of errors: default; errors are not reported using the TDA9951 Data.err service or common error register errors reported using the TDA9951 Data.err service or common error register sets the polarity of the INT output when it is active: 0 1 default; the I2C_INT output is active-LOW the I2C_INT output is active-HIGH these bits set the CEC retry count used by the TDA9951. The maximum value is 5; values greater than 5 give 5 retries: 0 to 4 5 6 to 7 valid retry count default; maximum valid retry count accepted as 5 retries
Symbol not used ENABLE_ ERROR
1 3 INT_POL R/W
2 to 0
RETRY[2:0]
R/W
Communication between the TDA9951 and the host processor for the data registers is carried out using information frames transferred using the common data register subaddress range 07h to 19h. The common data registers CDR0 to CDR18 are described in detail in Section 8.5.
8.5 Data register protocol
Before a frame is read or written, the host processor must set the REG_PTR field in the address pointer register to the base data register address. Message transfers can only start from the first data register at address 07h. They must not start from higher addresses because message transfer must be in complete sequences and not in fragments. Each frame consists of a byte count, service selector, followed by zero or more parameters as shown in Figure 3.
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TDA9951
CEC/I2C-bus translator
Register 07h FrameByteCount
Register 08h ServiceSelector
Register 09h [Parameter]
[...] [...]
[...] [...]
001aai277
Fig 3.
Frame format for the data register protocol
The FrameByteCount is the number of bytes in the frame (including the FrameByteCount itself). The service is specified by the ServiceSelector (see Table 15). If an unused ServiceSelector is sent to the TDA9951, it responds with the confirm Bad.req service (see Table 17, Table 28, Table 32 and Table 36). The remaining bytes of the frame can contain up to 17 parameters associated with the service. Services do not have optional parameters. The TDA9951 only accepts one outstanding request. The data service provided using the common data registers comprises:
* Host to the TDA9951: requests.
- A request is sent from the host to the TDA9951 or to a device on one of its interfaces.
* TDA9951 to the host: confirmations, indications and errors.
- Confirmations are used to answer requests for status and flow control, to show if the request has been passed on to the intended recipient or if it has been accepted/rejected. - Indications are messages from the TDA9951 interface to the host. Generally relating to normal operation. - Errors are messages from a TDA9951 to the host. Generally relating to an error state. Table 15 lists the data services and their ServiceSelector values. The contents of each service is described in detail in the following Protocol Layer sections.
Table 15. 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 81h KEYData.req KEYData.cnf CECData.ind SBYData.req SBYData.cnf RTCData.req RTCData.cnf VFDData.req VFDData.cnf Data services Host to TDA9951 CECData.req CECData.cnf TDA9951 to host Message type request confirmation request confirmation request confirmation request confirmation request confirmation CEC indication, no error
ServiceSelector
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CEC/I2C-bus translator
Data services ...continued Host to TDA9951 TDA9951 to host CECData.err CECData.ier RTCData.ind IRData.ind KEYData.ind Message type no indication, error indication and error RTC alarm indication, no error IR command indication, no error KEY indication, no error
Table 15. 82h 83h 84h 85h 86h
ServiceSelector
8.5.1 CECData.req service
This CECData.req request service is sent from the host to the TDA9951 instructing it to transmit an addressed or broadcast message. If the correct signal free time rules are met, transmission of the CEC message starts as soon as the complete message is received by the TDA9951. Table 16 shows the frame byte for the service.
Table 16. Register 07h 08h 09h 0Ah to 18h Frame Bytes for CECData.req service Frame Byte ServiceSelector AddressByte DataBytes Value 00h Comments CECData.req source and destination logical addresses in the format: SSSS DDDD zero to fifteen bytes up to the FrameByteCount - 3 data length FrameByteCount 03h to 18h
8.5.2 CECData.cnf service
Using this service the TDA9951 informs the host of the success or failure of a CECData.req service. The frame bytes are shown in Table 17.
Table 17. Register 07h 08h 09h Frame Bytes for CECData.cnf service Frame Byte FrameByteCount ServiceSelector ResultCode 00h 80h 81h 82h 83h 84h 85h 86h Value 03h 01h CECData.cnf a value indicating the result of the transmission success CEC in off-state Bad.req service failed; unable to access CEC line failed; arbitration error failed; bit timing error failed; destination address not acknowledged failed; data byte not acknowledged Comments
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CEC/I2C-bus translator
8.5.3 CECData.ind service
Using this service the TDA9951 transfers a CEC indication message to the host which was received from another remote device. The frame bytes are shown in Table 18.
Table 18. Register 07h 08h 09h 0Ah to 18h Frame Bytes for CECData.ind service Frame Byte FrameByteCount ServiceSelector AddressByte DataBytes Value 03h to 12h 81h CECData.ind source and destination logical addresses in the format: SSSS DDDD zero to fifteen bytes up to the FrameByteCount - 3 data length Comments
8.5.4 CECData.err service
Using this service, the TDA9951 alerts the host to a CEC error condition. There are no parameters. The host should read the Common Error Register (CER) for details of the error. Only active when bit 4 of the Common Configuration Register (CCONR) is set to enable error indications. The frame bytes for the service are shown in Table 19.
Table 19. Register 07h 08h Frame Bytes for CECData.err service Frame Byte FrameByteCount ServiceSelector Value 02h 82h CECData.err Comments
8.5.5 CECData.ier service
Using this service, the TDA9951 transfers a CEC message to the host which was received from another remote device. In addition, it alerts the host to a CEC error condition. The host should read the TDA9951 Common Error Register (CER) for details of the error. Only active when bit 4 of the CEC Common Configuration Register (CCONR) is set to enable error indications. The frame bytes are listed in Table 20.
Table 20. Register 07h 08h 09h 0Ah to 19h Frame Bytes for CECData.ier service Frame Byte FrameByteCount ServiceSelector AddressByte DataBytes Value 03h to 13h 83h CECData.ier source and destination logical addresses in the format: SSSS DDDD zero to sixteen bytes up to the FrameByteCount - 3 data length Comments
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CEC/I2C-bus translator
8.6 Example communication sequences
8.6.1 Notes on writing the CEC common data registers
Common data registers should be written in one contiguous operation between a START and STOP condition. The write action starts from the first data register and includes all registers indicated by the contents of that data register. The length of the message is given by the byte in the first data register. This is at least three for the shortest message. Lower values than three indicate an invalid message. Data registers ignore data in the following cases:
* When fewer data registers are written than the number indicated by the first data
register. The partial message is ignored and a confirmation is not returned.
* When more data registers are written than the number indicated by the first data
register. The message is processed once the message's last data register is written but the extra bytes written are ignored.
* When the highest data register is written and more message bytes are indicated by
the first data register. The message is processed once the highest data register is written but the extra bytes written are ignored.
8.6.2 Notes on reading the CEC common data registers
Data registers should be read in one contiguous operation, starting from the first data register up to the last register indicated by the Data register. The data registers can only contain valid messages when the INT line and the INT bit in the TDA9951 status register are set. Typical read situations:
* When data registers are read and the INT line is not set, the first data register
contains 0 (no bytes to read). Any additional read sequences before a STOP condition return the value FFh.
* When the host writes to data registers and starts reading without first resetting the
address pointer register, the read sequence commences from the first data register.
* When reading stops before all indicated data registers are read, the TDA9951 resets
the INT line, ignores the message and the message is lost.
* When reading continues for more data registers than indicated by the first data
register, the value FFh is read. The INT line is reset when the last valid data register for the message is read.
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8.6.3 Communication use cases
S
SLAVE ADDRESS
W
A
0000 0000
A
Sr
SLAVE ADDRESS
R
A

A
P
write address pointer '0' (write) Sr = repeated START condition
'1' (read)
read status
from master to slave
from slave to master
001aag925
A = acknowledge (SDA = LOW). S = START condition. P = STOP condition.
Fig 4.
Host reads TDA9951 status register after setting address pointer
S
SLAVE ADDRESS
R
A

A
P
'1' (read)
read status
from master to slave
from slave to master
001aag926
A = acknowledge (SDA = LOW). S = START condition. P = STOP condition.
Fig 5.
Host reads TDA9951 status register without setting address pointer (pointer was at 0 already)
S
SLAVE ADDRESS
W
A
0000 0100
A
Sr
SLAVE ADDRESS
R
A

A
....

A
P
write address pointer '0' (write) Sr = repeated START condition
'1' (read) read address H
read address L
from master to slave
from slave to master
001aag927
A = acknowledge (SDA = LOW). S = START condition. P = STOP condition. R = read. W = write.
Fig 6.
Host reads address ACK registers after setting address pointer
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CEC/I2C-bus translator
S
SLAVE ADDRESS
W
A
0000 0110
A

A
P
'0' (write) write address pointer
write config
from master to slave
from slave to master
001aag928
A = acknowledge (SDA = LOW). S = START condition. P = STOP condition. W = write.
Fig 7.
Host writes configuration register after setting address pointer
.....

A

A

A
P
write data 17h write data 18h from master to slave
write data 19h
from slave to master
001aag929
A = acknowledge (SDA = LOW). A = not acknowledge (SDA = HIGH). P = STOP condition.
Fig 8.
Host writes last three data registers
8.7 I2C command examples
8.7.1 Initialization
After a reset, configure the TDA9951 with its logical address or addresses (as required):
* I2C_WRITE: 04h, 00h, 08h
Set address pointer to 04h (ACKH), set ACKH to 00h and set ACKL to 08h (example). The TDA9951 is now configured to acknowledge messages to logical address 3 (Tuner 1). Remark: It is then mandatory to set the TDA9951 to the ON state as follows:
* I2C_WRITE: 03h, 40h
Set address pointer to 03h (CCR) and set CCR to 40h. The TDA9951 is now enabled. Messages addressed to logical address Tuner 1 is acknowledged and forwarded to the host processor.
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CEC/I2C-bus translator
8.7.2 Sending CEC messages
Example: the host processor of playback device 1 wishes to send the message to TV:
* I2C_WRITE: 00h; I2C_READ, I2C_READ, ...
Set address pointer to 00h (CSR) and read common status register. Repeat the read sequence until TDA9951 is no longer busy (bit 7 = 0).
* I2C_WRITE: 07h, 04h, 00h, 40h, 0Dh
Set address pointer to 07h (Data Register 1) and write data registers. FrameByteCount = 4, ServiceSelector = CECData.req, AddressByte = DVD/TV and DataByte = .
* Wait for INT line to be asserted
When TDA9951 has a response, it asserts the I2C_INT line (could also poll bit 6 of CSR).
* I2C_WRITE: 07h; I2C_READ: 03h, 01h, 00h
Set address pointer to 07h (Data Register 1) and read data registers. FrameByteCount = 3, ServiceSelector = CECData.cnf and ResultCode = Success.
8.7.3 Receiving CEC messages
Example: TV sends the message to Playback Device 1:
* INT line is asserted
The TDA9951 at playback device 1 has acknowledged the message from TV and it is now available for reading by the playback device 1 host processor.
* I2C_WRITE: 07h; I2C_READ: 04h, 81h, 04h, 83h
Set address pointer to 07h (Data Register 1) and read data registers. FrameByteCount = 4, ServiceSelector = CECData.ind, AddressByte = TV/DVD and DataByte = .
8.8 Infrared receiver interface
8.8.1 Infrared hardware
The input port pin IR_DAT is active LOW and receives demodulated infrared data from an external demodulator device that strips the 36 kHz infrared carrier. The output port pin IR_VAL is driven LOW for 65 ms after a valid frame is received enabling it to drive an external LED activity indicator. Wave form timing is achieved using the chip's capture and compare unit based on the defined timing limits.
* In RC5 mode, timing tolerances are checked and frames containing any bits outside
the limits are rejected.
* Start bits have wider timing tolerances than other bits to avoid false frame rejection. * In RC6 Mode 0, timing tolerances are checked and frames containing any bits outside
the limits are rejected.
* Dropout spikes of 60 s or less are ignored during start bit or leader pulse detection.
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CEC/I2C-bus translator
8.8.2 Protocol discrimination
The three protocol variants are automatically selected by measuring the length of the first active pulse, as follows:
Table 21. Protocol RC5 RC5 Enlarged RC6 Mode 0 Protocol discrimination Active pulse second half of start bit S1 second half of start bit S1 and first half of command bit /C6 first part of leader pulse Nominal Time range time (s) (s) 889 1778 2667 676 to 1306 1352 to 2178 2179 to 3360
8.8.3 IRData.ind service
This service is used to transfer an infrared remote control commands to the host. The frame bytes for the service are shown in Table 22. Remark: The SBYData.req request service configures some IRX commands to enter or leave Standby mode.
Table 22. Register 07h 08h 09h Frame Bytes for IRData.ind service Frame Byte FrameByteCount ServiceSelector CmdFlags 7 to 2 1 0 1 0 0Ah 0Bh CmdAddress CmdData 0 or 1 00h Bit Value 05h 85h IRData.ind bit flags associated with the command: unused; set to 0 protocol type RC5 RC6 a copy of the received Toggle bit command address byte command data or command byte Comments
8.9 Key matrix interface
8.9.1 Key matrix hardware
The Key Matrix Interface (KEY) is designed to manage up to 10 buttons. The key matrix interface uses five input lines (KROW0 to KROW4) and one output line (KCOL) to decode a matrix of up to ten normally open switch contacts. Contact de-bouncing is achieved by reading the input again after a nominal 20 ms period and discarding the event if the state changes in that time.
8.9.2 Key matrix decoding
The decoding algorithm is described in Application Note AN10184 (Connecting a keyboard to the LPC9xx microcontroller, 14/09/2002). Multiple simultaneous contact closure events are discarded.
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8.9.3 Key matrix encoding
The KROW0 to KROW4 input lines (matrix rows) are connected to the chip port 0. The port produces an interrupt when certain port inputs match or deviate from a set pattern. This allows the unused pins of port 0 to be masked out of this process and used for other purposes. The KCOL output line (matrix column) is used to identify which set of five switches the input contact closure belongs to. Key events are encoded as follows. The matrix rows are numbered 0 to 4 and the matrix columns 0 to 1. A contact closure is defined as the intersection of a row and column in the matrix:
Table 23. Column 0 0 0 0 0 Key matrix Row 0 1 2 3 4 Key ID 1 2 3 4 5 Column 1 1 1 1 1 Row 0 1 2 3 4 Key ID 6 7 8 9 10
8.9.4 KEYData.req service
Using this service the host requests the current matrix key switch states. The frame bytes for the service are shown in Table 24.
Table 24. Register 07h 08h Frame Bytes for KEYData.req service Frame Byte FrameByteCount ServiceSelector Value 02h 08h KEYData.req Comments
8.9.5 KEYData.cnf service
Using this service, the TDA9951 informs the host of the matrix key switch states after a KEYData.req service request. The frame bytes are shown in Table 25.
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Frame Bytes for KEYData.cnf service Frame Byte FrameByteCount ServiceSelector KeyStates1 7 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1 Bit Value Comments 04h 09h KeyData.cnf bit flags showing the states of key switches 1 to 8: key 8 open closed key 7 open closed key 6 open closed key 5 open closed key 4 open closed key 3 open closed key 2 open closed key 1 open closed bit flags showing the states of key switches 9 to 10 7 to 2 1 0 1 0 0 1 not used key 10 open closed key 9 open closed
Table 25. Register 07h 08h 09h
0Ah
KeyStates2
8.9.6 KEYData.ind service
Using this service, the TDA9951 transfers a key press or release command to the host. The frame bytes are listed in Table 26.
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Frame Bytes for KEYData.ind service Frame Byte FrameByteCount ServiceSelector KeyData 0 to 3 4 to 6 7 1 0 Bit Value 03h 86h KEYData.ind bit field associated with the key switch event: key code 1 to 10 not used key open closed Comments
Table 26. Register 07h 08h 09h
8.10 Real time clock interface
8.10.1 Real time clock hardware
The Real Time Clock (RTC) interface communicates with a software clock-calendar running in the TDA9951 which uses the dedicated 23-bit RTC. The RTC timer is set to generate a 1 s interrupt. When the power source changes from power supply to battery, the PSEN input goes LOW. All interface and alarm/timer activity is stopped. The chip switches to low-power mode but continues to count RTC timer ticks. The host can read the clock-calendar on demand by using the RTCData.req request service. The current date and time is returned using the RTCData.cnf confirm service. The data registers are fixed during a read action ensuring a consistent time value is returned.
8.10.2 Clock-calendar
The 1 s event handler increments a long integer representing the number of seconds since the start of a time epoch. It also manages any active alarm and timers. The date and time fields in the request and confirmation services are converted to and from the long integer using code adapted from the "Maxim/Dallas Semiconductor application note 3721 Interfacing the DS1318 with an 8051 type Microcontroller, 9/12/2005".
8.10.3 Alarm
Only one alarm is active at a time with the clock-calendar and timers. The alarm is triggered when the real-time clock matches all date and time bytes set in an active alarm request. Setting an alarm replaces a previously set alarm. Alarms are cancelled by clearing the alarm active bit in the RTCData.req ServiceFlags byte. The Date and time bytes in RTCData.req are ignored if the active bit is cleared. Alarms are not active after a power-up or reset. An alarm sets Standby mode when its standby bit in the RTCData.req ServiceFlags byte is set. An alarm triggered in Standby mode exits and its standby bit is not set.
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8.10.4 Timers
A maximum of two timers may be simultaneously active with the clock-calendar and alarm. Each timer may be either one-shot or periodic.
* One-shot timers are triggered when the real-time clock matches the current time plus
the time and day bytes set by an active timer request.
* Periodic timers work in the same way but are triggered repeatedly at the specified
interval. The timer resolution is 1 s and allowed timer interval range is from 1 s up to 31 days, 23 hours, 59 minutes and 59 s. Setting timer 1 replaces the previous timer 1 setting but does not change timer 2 or a pending alarm. Timer 2 functions in the same way. Timers are stopped by clearing its respective timer active bit in the RTCData.req ServiceFlags byte. Date and time bytes in RTCData.req are ignored when the active bit is clear. After power-up and reset, the timers are not active. A timer sets Standby mode if its standby bit is set in the RTCData.req ServiceFlag byte. Timers triggered in Standby mode exits Standby mode when the respective standby bit is not set.
8.10.5 RTCData.req service
This service is used to read or set the clock date and time, to set an alarm or to set the timers. The frame bytes are listed in Table 27. The ServiceType byte determines the action to be performed. When the clock is read, all other bytes are ignored and can be set to 00h. When a timer is set, the Month and Year bytes are ignored and can be set to 00h.
Table 27. Register 07h 08h 09h Frame Bytes for RTCData.req service Frame Byte FrameByteCount ServiceSelector Service Type Bit Value 0Ah 04h 00h 01h RTCData.req read the clock date and time. All following bytes in this frame are not used, set to 00h set the clock date and time. Uses all date and time bytes but the ServiveFlags byte is not used set the alarm date and time. Uses all date and time bytes; standby operation is set by ServiceFlags set timer 1 to current time plus Day, Hour, Minute and Second bytes. Month and Year bytes not used; standby and periodic operation are set by ServiceFlags set timer 2 to current time plus Day, Hour, Minute and Second bytes. Month and Year bytes not used; standby and periodic operation are set by ServiceFlags Comments
02h
03h
04h
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Frame Bytes for RTCData.req service ...continued Frame Byte ServiceFlags Bit 7 to 3 2 0 1 1 0 0 1 0 1 Value Comments not used not used for alarm one-shot timer periodic timer normal standby alarm or timer stopped alarm or timer active
Table 27. Register 0Ah
0Bh 0Ch 0Dh 0Eh 0Fh 10h
Year Month Day Hour Minute Second
00h to 99h Year 2000 to 2099 01h to 12h Month 1 (January) to 12 (December) 01h to 31h Day 1 to 31 00h to 23h Hour 0 to 23 00h to 59h Minute 0 to 59 00h to 59h Second 0 to 59
8.10.6 RTCData.cnf service
Using this service the TDA9951 informs the host of the success or failure of a RTCData.req service and always returns the current date and time. The frame bytes are shown in Table 28.
Table 28. Register 07h 08h 09h Frame Bytes for RTCData.cnf service Frame Byte ServiceSelector ResultCode 00h 81h 90h 91h 92h 93h 94h 95h 96h 0Ah 0Bh 0Ch 0Dh Year Month Day Hour 00h to 99h 01h to 12h 01h to 31h 00h to 23h Value 05h Comments RTCData.cnf A value indicating the result of the request success, time and date are valid Bad.req service time and date cannot be read, they have not been set failed; bad Year failed; bad Month failed; bad Day failed; bad Hour failed; bad Minute failed; bad Second Year 2000 to 2099 Month 1 (January) to 12 (December) Day 1 to 31 Hour 0 to 23 FrameByteCount 0Ah
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Frame Bytes for RTCData.cnf service ...continued Frame Byte Minute Second Weekday Value 00h to 59h 00h to 59h 01h to 07h Comments Minute 5 to 59 Second 0 to 59 Day 1 (Sunday) to 7 (Saturday). This is always calculated and never set.
Table 28. Register 0Eh 0Fh 10h
8.10.7 RTCData.ind service
This indication service is used to alert the host of an alarm or timer event. In doing so, it always returns the current date and time. The frame bytes are listed in Table 29. No Indication is sent to the host in Standby mode.
Table 29. Register 07h 08h 09h Frame Bytes for RTCData.ind service Frame Byte FrameByteCount ServiceSelector ServiceType Bit Value 0Bh 84h 02h 03h 04h 0Ah ServiceFlags 7 to 3 2 0 1 1 0 0Bh 0Ch 0Dh 10h 11h Year Month Day Hour Weekday 0 1 0 1 00h to 99h 01h to 12h 01h to 31h 00h to 23h 01h to 07h RTCData.ind alarm event timer 1 event timer 2 event not used not used for alarm one-shot timer periodic timer normal standby alarm or timer stopped alarm or timer active Year 2000 to 2099 Month 1 (January) to 12 (December) Day 1 to 31 Hour 0 to 23 Day 1 (Sunday) to 7 (Saturday). Always calculated, never set Comments
8.11 Standby interface
8.11.1 Standby hardware
The SBY output is asserted to set the host or other CE device to lower-power operation. Due to the continuous interface monitoring required in this mode, the IC itself does not operate in low-power mode. However, PSEN input is driven LOW it operates in low-power mode). In Standby mode, no indication services are sent to the host.
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Standby mode changes Event Power-up CEC or IRX or KEY interface receives a configured wake-up command RTC interface raises a wake-up alarm Host sets SBY bit in CCR register CEC or IRX or KEY interface receives a configured Standby command RTC interface raises a Standby alarm PSEN input goes low New mode Standby On Standby Off SBY pin HIGH LOW
Table 30. Current mode Undefined
Standby On
Standby Off
Standby On
HIGH
8.11.2 SBYData.req service
Using this service the TDA9951 is instructed to enter or exit Standby mode when certain CEC opcodes, IR commands or key events occur. These three sources can have up to eight commands/events that can enter or leave Standby mode. A separate SBYData.req service must be sent from the host for each source. In addition, each IR command source also requires the corresponding address byte and flags byte are sent as separate requests. A received IR command must match on all three parameters (command, address and flags bytes) to trigger the Standby mode state change. The frame bytes are listed in Table 31.
Table 31. Register 07h 08h 09h Frame Bytes for SBYData.req service Frame Byte FrameByteCount ServiceSelector CmdSource Value 13h 06h 01h 02h 03h 04h 05h 0Ah StandbyCmd1 01h 01h to FFh 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h
TDA9951_1
Comments SBYData.req CEC; command codes are Opcodes 00h to FFh KEY; command codes key IDs in 0 IRX; command codes are commands 00h to FFh IRX; command codes are addresses 00h to FFh IRX; command codes are flags 00h to FFh for all command bytes: unused Valid user defined user defined user defined user defined user defined user defined user defined user defined
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StandbyCmd2 StandbyCmd3 StandbyCmd4 StandbyCmd5 StandbyCmd6 StandbyCmd7 StandbyCmd8 WakeupCmd1
-
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Frame Bytes for SBYData.req service ...continued Frame Byte WakeupCmd2 WakeupCmd3 WakeupCmd4 WakeupCmd5 WakeupCmd6 WakeupCmd7 WakeupCmd8 Value Comments user defined user defined user defined user defined user defined user defined user defined
Table 31. Register 13h 14h 15h 16h 17h 18h 19h
8.11.3 SBYData.cnf service
Using this service the TDA9951 informs the host of the success or failure of the SBYData.req service. The frame bytes are shown in Table 32.
Table 32. Register 07h 08h 09h Frame Bytes for SBYData.cnf service Frame Byte FrameByteCount ServiceSelector ResultCode 00h 81h A0h Value 03h 07h SBYData.cnf the result of the request success Bad.req service bad CmdSource Comments
8.12 Vacuum fluorescent display interface
8.12.1 VFD hardware
The output lines VFD_DAT, VFD_CLK, VFD_STR and VFD_BLK use an industry-standard serial protocol common to several driver chip manufacturers, such as Allegro Microsystems for more details see the "Data sheet 6810, DABiC-IV 10-bit serial-input, latched source driver, Allegro Microsystems, 26182.124E". The external driver chip latches the serial data and handles the high voltage I/O needed by VFD devices. A timer is used to output data at a constant rate, one grid at a time, to support multiplexed displays. Each grid must be refreshed at least 30 times a second to avoid display flicker. Non-multiplexed displays are not refreshed.
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8.12.2 VFD driver connection topologies
8.12.2.1 VFD driver device
CLOCK
VDD
LOGIC SUPPLY SERIAL DATA OUT
SERIAL DATA IN STROBE
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
BLANKING MOS BIPOLAR VSS GROUND OUT1 OUT2 OUT3 OUTN LOAD SUPPLY
001aai278
Fig 9.
VFD driver device
The four-wire serial interface sends data to the external driver device as follows: 1. The TDA9951 sets its VFD_DAT line to the required level and toggles its clock VFD8CLK output for each bit. These are connected to the device serial data in and Clock lines. 2. Data clocked in on the serial data in is moved to the serial data out when the shift register is full to allow driver cascading. This feeds the next drivers serial data in. 3. When all bits have been clocked into all drivers, the TDA9951 toggles VFD_STR which in turn toggles the device strobe line. 4. The TDA9951 VFD_BLK line drives the device blanking line which turns all driver outputs on or off. 8.12.2.2 Static drive
VFD_CLK VFD_DAT FPP(2) VFD_STR VFD_BLK CLOCK SERIAL DATA IN STROBE BLANKING
001aai279
(1)
UCN5810AF
UCN5810AF
(1) One latched driver line for every display anode; the grids are permanently powered. (2) The Front Panel Processor (FPP) is the TDA9951.
Fig 10. Static drive
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The driver outputs are connected to each separate display segment in one-grid displays.
* All data bits on VFD_DAT for every display segment are clocked in by VFD_CLK. * VFD_STR is pulsed * The required display segments are now lit with without the need for further control
actions. - Advantage: data is only clocked out to the display when the host changes the data. - Disadvantage: more driver devices and I/O lines are required for a given size. 8.12.2.3 Multiplexed drive
(1)
VFD_CLK VFD_DAT FPP(3) VFD_STR VFD_BLK CLOCK SERIAL IN STROBE BLANKING
001aai280
(2)
UCN5810AF
(1) Segment lines are connected to all corresponding anodes in a character position. (2) Grid lines drive each character. (3) The Front Panel Processor (FPP) is the TDA9951.
Fig 11. Multiplexed drive
A multiplexed scheme can use the same four wire interface for displays with multiple grids. In this case, only one character grid is enabled at a time together with the correct segment.
8.12.3 Host request bit mapping to clocked output bits
The SegmentByte value in the VFDData.req request form a bit array holding one or more grids of segment data. 8.12.3.1 Static drive all VFDData.req SegmentByte bits are clocked out once as soon as the last request in a series is received, no extra grid bits are sent by the TDA9951 for a one grid static display:
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TotalGrids = 1: STATIC DRIVE One group of segment bits VFDData. req b7 b6 b5 b4 b3 b2 b1 b0 SegmentByte1 to SegmentByte15 (controlling 120 VFD segments)
001aai281
VFD_Data Line Up to 255 segment bits from a series of Requests, clocked out in sequence
Fig 12. Static drive
8.12.3.2
Multiplexed drive Displays with more than one grid are multiplexed. The host manages the VFDData.req SegmentByte bits in groups of successive grids. Each of segment bits is padded to occupy the total number of SegmentByte locations, enabling easy specification of a subset of grids by SegmentByteOffset and FrameByteCount in the request. A large display may be driven in the same way by multiple requests. The TDA9951 is responsible for clocking out the grid bits, either before or after the request's segment bits, based on the GridMuxMode. Only one grid is set, corresponding to the grid group that is clocked out from the request. The TDA9951 repeats this procedure indefinitely.
TotalGrids > 1: MULTIPLEX DRIVE
VFDData. req b7 b7 b7 b7 b7 b7 b7 b7 b6 b6 b6 b6 b6 b6 b6 b6 b5 b5 b5 b5 b5 b5 b5 b5 b4 b4 b4 b4 b4 b4 b4 b4 b3 b3 b3 b3 b3 b3 b3 b3 b2 b2 b2 b2 b2 b2 b2 b2 b1 b1 b1 b1 b1 b1 b1 b1 b0 b0 b0 b0 b0 b0 b0 b0
Grid bits for each group Multiplex group 1 Multiplex group 2 Multiplex group 3 Multiplex group 4
VFD_Data Line
A group of segment bits and all grid bits are clocked out in one multiplex cycle
Example: 4 grids x 11 segments, in 4 groups of 11 bits each padded to 2 bytes. Grid bits are clocked out after segment bits, grid 1 last.
001aai282
Fig 13. Grid bits clocked out after the segment bits
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Segment lines
Character 1 Character 2 Character 3 Character 4
Grid lines
001aai283
(1) TDA9951 automatically sets the grid lines before the segment lines with grid 1 as the last (GridMuxMode = 1).
Fig 14. Output of four multiplex cycles comprising four characters
8.12.4 Multiplex drive timing
Table 33 shows the maximum number of segments supported for each number of grids, the timer interrupt rate and number of requests required. It assumes 5 s per bit for setting the data line, pulsing the clock line to send each grid and the segment bit to the external driver.
Table 33. Multiplex drive timing Recommended number of segments 255 248 157 121 95 74 73 54 53 40 39 28 27 26 17 16 15 14 13 12 7 Timer interrupt rate (Hz) N/A 80 125 160 200 250 250 320 320 400 400 500 500 500 625 625 625 625 625 625 800 Grid update rate (31 Hz to 42 Hz) N/A 40 41.66 40 40 41.66 35.71 40 35.55 40 36.36 41.66 38.36 38.36 41.66 39.06 36.76 34.72 32.89 31.25 38.09 Requests for maximum segments 3 5 4 5 4 4 5 4 5 4 4 4 4 4 3 3 3 3 3 3 2
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Grids (character positions) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
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8.12.5 Multiplex drive pitfalls
There are several potential pitfalls to avoid with a multiplexed drive:
* Multiplexing is too slow causing the display to flicker
Solution: light each character grid at least 30 times a second
* If a one character grid is immediately enabled after the previous grid, ghosting may be
seen where the drives for the previous character segment are enabled for a short time during the new character Solution: use an inter-character blank time at the start of each grid time slot by setting VFD_BLK for 10 s to 50 s.
* If multiplexing stops, display damage can occur
Solution: assert VFD_BLK if a reset occurs or use an external watchdog protection circuit. See Noritake Itron "Chip in glass Driver VFD application note" for more detailed information.
* The contents of the VFD driver are undefined and may result in irrelevant data display
during start-up Solution: Set VFD_BLK during the first multiplex cycle
8.12.6 VFDData.req service configuration
Using this service the host can send configuration data to the TDA9951. Only one configuration service is acted on after power-up because the TDA9951 does not support dynamic display changes. The frame bytes are shown in Table 34. When the request is received, the VFD_BLK output is reset to a state based on the current blanking polarity.
Table 34. 07h 08h 09h 0Ah Frame Bytes for VFDData.req service - configuration Value 07h 02h 00h 1 to 20 1 >1 0Bh SegmentsPerGrid VFDData.req configuration request Total grids: VFD is statically driven VFD is multiplexed Comments FrameByteCount ServiceSelector ServiceType TotalGrids
Register Frame Byte
1 to 255 segments or dots per grid. See Table 33 for the maximum SegmentsPerGrid value for each TotalGrids value 0 to 3 0 1 2 3 control how the TDA9951 clocks out grid control bits for multiplexed displays (Ignored when TotalGrids = 1): grids clocked before segments, 1 first grids clocked before segments, 1 last grids clocked after segments, 1 first grids clocked after segments, 1 last VFD_BLK line is active LOW VFD_BLK line is active HIGH (default)
0Ch
GridMuxMode
0Dh
BlankingPolarity
0 1
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8.12.7 VFDData.req service segment data
Using this service the host sends display segment data to the TDA9951. The frame bytes for this function are shown in Table 35. Multiple requests are used to send segment data that is longer than one request. SegmentByteOffset bit 7 is set only in the last request. If this request is received while the VFD bit in the common control register is clear, the data is stored but the display is not driven until the VFD bit is set.
Table 35. 07h 08h 09h 0Ah Frame Bytes for VFDData.req service segment data Bit Value 05h to 13h 02h 01h 6 to 0 00h to 7Fh Comments 1 segment byte (05h) to 15 bytes (13h) VFDData.req segment data request byte offset applied to SegmentByte1 for displays that require multiple requests request 1; SegmentOffset = 0 request 2; SegmentOffset = 15 etc. a request can also update part of a display, e.g. to set SegmentByte2, SegmentByte3: SegmentByteOffset = 1 FrameByteCount = 6 7 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h SegmentByte1 SegmentByte2 SegmentByte3 SegmentByte4 SegmentByte5 SegmentByte6 SegmentByte7 SegmentByte8 SegmentByte9 SegmentByte10 SegmentByte11 SegmentByte12 SegmentByte13 SegmentByte14 SegmentByte15 0 or 1 00h to FFh indicates the last request in a multi-request series segment bits 1 to 8 clocked out in sequence start in with bit 1 segment bits 9 to 16 segment bits 17 to 24 segment bits 25 to 32 segment bits 33 to 40 segment bits 41 to 48 segment bits 49 to 56 segment bits 57 to 64 segment bits 65 to 72 segment bits 73 to 80 segment bits 81 to 88 segment bits 89 to 96 segment bits 97 to 104 segment bits 105 to 112 segment bits 113 to 120 FrameByteCount ServiceSelector ServiceType SegmentByteOffset
Register Frame Byte
8.12.8 VFDData.cnf service
Using this service the TDA9951 informs the host of the success or failure of a VFDData.req service. It is mainly used for flow control and ensures the host does not send new data before the previous request has completed. The frame bytes are shown in Table 36.
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Frame Bytes for VFDData.cnf service Frame Byte FrameByteCount ServiceSelector ResultCode 00h 80h 81h B0h B1h B2h B3h B4h B5h B6h B7h Value 03h 03h VFDData.cnf A value indicating the result of the request Success VFD in Off state bad.req service bad ServiceType bad TotalGrids bad SegmentsPerGrid SegmentsPerGrid is too large for TotalGrids bad GridMuxMode bad BlankingPolarity bad SegmentByteOffset segment service sent before Configuration service Comments
Table 36. Register 07h 08h 09h
9. Limiting values
Table 37. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Tamb(bias) Tstg IOH IOL IIO(tot) VDD(xtal) Vn Ptot Parameter bias ambient temperature storage temperature HIGH-level output current LOW-level output current total input/output current crystal supply voltage voltage on any other pin total power dissipation on pins XTAL1, XTAL2 except pins XTAL1, XTAL2, VDD based on package heat transfer, not device power consumption all input/output pin all input/output pin Conditions operating Min -55 -65 Max +125 +150 20 20 100 VDD + 0.5 3.5 1.5 Unit C C mA mA mA V V W
[1]
Parameters are valid for Tamb = -40 C to +85 C temperature range, unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
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CEC/I2C-bus translator
10. Static characteristics
Table 38. Static characteristics VDD = 2.4 V to 3.6 V; Tamb = -40 C to +85 C for industrial application; unless otherwise specified. Symbol IDD Parameter supply current Conditions Operating mode; VDD = 3.6 V; fosc = 12 MHz Idle mode; VDD = 3.6 V; fosc = 12 MHz Power-down mode, voltage comparators powered down; VDD = 3.6 V Total Power-down mode; VDD = 3.6 V dV/dt VDD VRAM Vth(HL) Vth(LH) VIL VIH Vhys VOL rate of change of voltage supply voltage RAM keep-alive voltage HIGH to LOW threshold voltage LOW to HIGH threshold voltage LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage except pins SCL, SDA except pins SCL, SDA SCL, SDA only SCL, SDA only port 1 IOL = 20 mA; VDD = 2.4 V to 3.6 V all ports, all modes except high-Z IOL = 3.2 mA; VDD = 2.4 V to 3.6 V all ports, all modes except high-Z VOH HIGH-level output voltage IOH = -20 A; VDD = 2.4 V to 3.6 V; all ports, quasi-bidirectional mode IOH = -3.2 mA; VDD = 2.4 V to 3.6 V; all ports, push-pull mode IOH = -10 mA; VDD = 3.6 V; all ports, push-pull mode VDD(xtal) Vn Ci IIL ILI IT(HL) crystal supply voltage voltage on any other pin input capacitance LOW-level input current input leakage current HIGH to LOW transition current logical 0; VI = 0.4 V VI = VIL, VIH or Vth(HL) all ports; VI = 1.5 V at VDD = 3.6 V on pins XTAL1, XTAL2; with respect to VSS except pins XTAL1, XTAL2, VDD; with respect to VSS
[5] [4] [2]
Min -
Typ[1] 11 3.25 55
Max 18 5 80
Unit mA mA A
[2]
[2]
[3]
2.4 1.5 0.22VDD -0.5 0.7VDD -
1 3.0 0.4VDD 0.6VDD 0.2VDD 0.6
5 2 50 3.6 0.7VDD
A mV/s mV/s V V V V
rise rate of VDD fall rate of VDD
+0.3VDD V 5.5 1.0 V V V
-
0.2
0.3
V
VDD - 0.3
VDD - 0.2
-
V
VDD - 0.7
VDD - 0.4
-
V
-0.5 -0.5 -30
3.2 -
+4.0 +5.5 15 -80 10 -450
V V V pF A A A
[6] [7] [8] [9]
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Product data sheet
Rev. 01 -- 7 August 2008
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NXP Semiconductors
TDA9951
CEC/I2C-bus translator
Table 38. Static characteristics ...continued VDD = 2.4 V to 3.6 V; Tamb = -40 C to +85 C for industrial application; unless otherwise specified. Symbol Rpu(int) Vbo Vref(bg) TCbg Tamb
[1] [2] [3] [4] [5]
Parameter internal pull-up resistance brownout voltage band gap reference voltage band gap temperature coefficient ambient temperature
Conditions pin RST_N 2.4 V < VDD < 3.6 V; with BOE = 1, BOPD = 0
[10]
Min 10 2.40 1.11 -40
Typ[1] 1.23 10 -
Max 30 2.70 1.34 20 +85
Unit k V V 10-6/C C
Typical ratings are not guaranteed. The values listed are at room temperature and VDD = 3.3 V. The IDD in Operating mode, Idle mode and Power-down mode specifications are measured using an external clock with the following functions disabled: comparators, real-time clock and watchdog timer. The IDD total Power-down mode specification is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect and watchdog timer. See Section 9 "Limiting values" on page 32 for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may exceed the related specification. This specification can be applied to pins which have an A/D input or analog comparator input functions and when the pin is not used for those analog functions. When the pin is used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with respect to VSS. Pin capacitance is characterized but not tested. Measured with port in quasi-bidirectional mode. Measured with port in high-impedance mode. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from HIGH to LOW. This current is highest when VI is approximately 2 V.
[6] [7] [8] [9]
[10] BOE is brownout enabled and BOPD is the state of brownout detection (0 = active).
11. Dynamic characteristics
Table 39. Dynamic characteristics (12 MHz) VDD = 2.4 V to 3.6 V; Tamb = -40 C to +85 C for industrial applications; fosc = 12 MHz (crystal); unless otherwise specified. Symbol Glitch filter tgr tsa glitch rejection time signal acceptance time pin RST_N any pin except RST_N pin RST_N any pin except RST_N I2C-bus: pins SDA and SCL; 5 V tolerant fclk clock frequency Standard mode Fast mode 100 400 kHz kHz 125 50 50 15 ns ns ns ns Parameter Conditions Min Typ Max Unit
TDA9951_1
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Product data sheet
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NXP Semiconductors
TDA9951
CEC/I2C-bus translator
12. Application information
External IR Source VDD
100 470 18 MHz
22 pF
22 pF
VDD
IR Source Jumper 18 XTAL1 28 IR_DAT 29 XTAL2 IR_VAL 27
4.7 F
VFD Display Driver Allegro A6810 (Display not shown) VBB Load Supply VDD 17 CLOCK DATA IN STROBE BLANK 5 VDD 6
IR Demodulator Vishay TSOP34136
21 24 23 22 20 19 15
VDD KROW0 KROW1 KROW2 KROW3 KROW4 KCOL PSEN
VFD_CLK VFD_DAT VFD_STR VFD_BLK VSS
1 2 13 14 7
4 16 7 15
CEC_IN CEC_OUT
10 5
47 k
27 k
Key Matrix VBB
16
220 pF
1N4148
VDD VDD SDA SBY SCL INT A0 RST_N
18 k 100 k BC337 220 pF
60 V 3.9 V 3.9 V battery 1N4148 x3 0V Power VSS
26
11
12
4
3
6 VDD
220
A0 Jumper
10 k
VSS
Host Interface
10 F
Reset
CEC bus
001aai284
Fig 15. Application diagram
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Product data sheet
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NXP Semiconductors
TDA9951
CEC/I2C-bus translator
13. Package outline
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1
D
E
A
X
c y HE vMA
Z
28
15
Q A2 pin 1 index A1 (A 3) A
Lp L detail X
1
e bp
14
wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.5 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 16. Package outline SOT361-1 (TSSOP28)
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Product data sheet
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NXP Semiconductors
TDA9951
CEC/I2C-bus translator
14. Abbreviations
Table 40. Acronym CE CEC DVD EOM FPP HDMI IR RGB RTC TV VFD YCbCr Abbreviations Description Consumer Electronics Consumer Electronics Control Digital Versatile Disc End Of Message Front Panel Processor High-Definition Multimedia Interface InfraRed Red Green Blue Real Time Clock TeleVision Vacuum Fluorescent Display Y = Luminance, Cb = Chroma blue, Cr = Chroma red
15. Revision history
Table 41. Revision history Release date 20080807 Data sheet status Product data sheet Change notice Supersedes Document ID TDA9951_1
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Product data sheet
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NXP Semiconductors
TDA9951
CEC/I2C-bus translator
16. Legal information 17. Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.1 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
17.2 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of
17.3 Licenses
ICs with RC5 functionality Purchase of an NXP Semiconductors IC with RC5 functionality does not convey an implied license under any trade secret, copyright, know-how or patent right to use this IC in any RC5 application. A license under applicable rights of Koninklijke Philips Electronics N.V. needs to be obtained via Philips Intellectual Property and Standards (www.ip.philips.com), e-mail: info.licensing@philips.com. ICs with RC6 functionality Purchase of an NXP Semiconductors IC with RC6 functionality does not convey an implied license under any trade secret, copyright, know-how or patent right to use this IC in any RC6 application. A license under applicable rights of Koninklijke Philips Electronics N.V. needs to be obtained via Philips Intellectual Property and Standards (www.ip.philips.com), e-mail: info.licensing@philips.com.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
TDA9951_1
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Product data sheet
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NXP Semiconductors
TDA9951
CEC/I2C-bus translator
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
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NXP Semiconductors
TDA9951
CEC/I2C-bus translator
19. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 I2C-bus slave address. . . . . . . . . . . . . . . . . . . . .6 I2C Register configuration . . . . . . . . . . . . . . . . .6 APR - Address pointer register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .7 CSR - Common status register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .7 CER - Common error register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .7 CVR - Common version register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .8 CCR - Common control register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .8 ACKH - CEC address ACK high register (address 04h) bit description . . . . . . . . . . . . . . .8 ACKL - CEC address ACK low register (address 05h) bit description . . . . . . . . . . . . . . .9 ADDR[14:0] definition . . . . . . . . . . . . . . . . . . . . .9 CCONR - Common configuration register (address 06h) bit description . . . . . . . . . . . . . . .9 Data services . . . . . . . . . . . . . . . . . . . . . . . . .10 Frame Bytes for CECData.req service . . . . . . .11 Frame Bytes for CECData.cnf service . . . . . . .11 Frame Bytes for CECData.ind service . . . . . . .12 Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Frame Bytes for CECData.err service . . . . . . . 12 Frame Bytes for CECData.ier service . . . . . . . 12 Protocol discrimination . . . . . . . . . . . . . . . . . . 17 Frame Bytes for IRData.ind service . . . . . . . . 17 Key matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Frame Bytes for KEYData.req service . . . . . . 18 Frame Bytes for KEYData.cnf service . . . . . . . 19 Frame Bytes for KEYData.ind service . . . . . . . 20 Frame Bytes for RTCData.req service . . . . . . 21 Frame Bytes for RTCData.cnf service . . . . . . . 22 Frame Bytes for RTCData.ind service . . . . . . . 23 Standby mode changes . . . . . . . . . . . . . . . . . 24 Frame Bytes for SBYData.req service . . . . . . 24 Frame Bytes for SBYData.cnf service . . . . . . . 25 Multiplex drive timing . . . . . . . . . . . . . . . . . . . . 29 Frame Bytes for VFDData.req service configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Frame Bytes for VFDData.req service segment data . . . . . . . . . . . . . . . . . . . . . . . . . 31 Frame Bytes for VFDData.cnf service . . . . . . . 32 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 32 Static characteristics . . . . . . . . . . . . . . . . . . . . 33 Dynamic characteristics (12 MHz) . . . . . . . . . 34 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 37
20. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4 Frame format for the data register protocol . . . . .10 Host reads TDA9951 status register after setting address pointer. . . . . . . . . . . . . . . . . . . . .14 Host reads TDA9951 status register without setting address pointer (pointer was at 0 already) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Host reads address ACK registers after setting address pointer . . . . . . . . . . . . . . . . . . . . . . . . . .14 Host writes configuration register after setting address pointer . . . . . . . . . . . . . . . . . . . . . . . . . .15 Host writes last three data registers . . . . . . . . . .15 VFD driver device . . . . . . . . . . . . . . . . . . . . . . . .26 Static drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Multiplexed drive . . . . . . . . . . . . . . . . . . . . . . . . .27 Static drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Grid bits clocked out after the segment bits. . . . .28 Fig 14. Output of four multiplex cycles comprising four characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fig 15. Application diagram . . . . . . . . . . . . . . . . . . . . . . . 35 Fig 16. Package outline SOT361-1 (TSSOP28) . . . . . . . 36
Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13.
continued >>
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Product data sheet
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NXP Semiconductors
TDA9951
CEC/I2C-bus translator
21. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 8.6.1 8.6.2 8.6.3 8.7 8.7.1 8.7.2 8.7.3 8.8 8.8.1 8.8.2 8.8.3 8.9 8.9.1 8.9.2 8.9.3 8.9.4 8.9.5 8.9.6 8.10 8.10.1 8.10.2 8.10.3 8.10.4 8.10.5 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Device addressing . . . . . . . . . . . . . . . . . . . . . . 5 Configuring the TDA9951 . . . . . . . . . . . . . . . . . 6 Using the INT line . . . . . . . . . . . . . . . . . . . . . . . 7 Register descriptions . . . . . . . . . . . . . . . . . . . . 7 Data register protocol . . . . . . . . . . . . . . . . . . . . 9 CECData.req service . . . . . . . . . . . . . . . . . . . 11 CECData.cnf service . . . . . . . . . . . . . . . . . . . 11 CECData.ind service . . . . . . . . . . . . . . . . . . . 12 CECData.err service. . . . . . . . . . . . . . . . . . . . 12 CECData.ier service . . . . . . . . . . . . . . . . . . . . 12 Example communication sequences . . . . . . . 13 Notes on writing the CEC common data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Notes on reading the CEC common data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Communication use cases . . . . . . . . . . . . . . . 14 I2C command examples . . . . . . . . . . . . . . . . . 15 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Sending CEC messages. . . . . . . . . . . . . . . . . 16 Receiving CEC messages . . . . . . . . . . . . . . . 16 Infrared receiver interface . . . . . . . . . . . . . . . . 16 Infrared hardware . . . . . . . . . . . . . . . . . . . . . . 16 Protocol discrimination . . . . . . . . . . . . . . . . . . 17 IRData.ind service . . . . . . . . . . . . . . . . . . . . . 17 Key matrix interface . . . . . . . . . . . . . . . . . . . . 17 Key matrix hardware . . . . . . . . . . . . . . . . . . . . 17 Key matrix decoding . . . . . . . . . . . . . . . . . . . . 17 Key matrix encoding . . . . . . . . . . . . . . . . . . . . 18 KEYData.req service . . . . . . . . . . . . . . . . . . . 18 KEYData.cnf service. . . . . . . . . . . . . . . . . . . . 18 KEYData.ind service. . . . . . . . . . . . . . . . . . . . 19 Real time clock interface. . . . . . . . . . . . . . . . . 20 Real time clock hardware . . . . . . . . . . . . . . . . 20 Clock-calendar . . . . . . . . . . . . . . . . . . . . . . . . 20 Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 RTCData.req service . . . . . . . . . . . . . . . . . . . 21 8.10.6 8.10.7 8.11 8.11.1 8.11.2 8.11.3 8.12 8.12.1 8.12.2 8.12.2.1 8.12.2.2 8.12.2.3 8.12.3 RTCData.cnf service . . . . . . . . . . . . . . . . . . . RTCData.ind service . . . . . . . . . . . . . . . . . . . Standby interface . . . . . . . . . . . . . . . . . . . . . . Standby hardware . . . . . . . . . . . . . . . . . . . . . SBYData.req service . . . . . . . . . . . . . . . . . . . SBYData.cnf service . . . . . . . . . . . . . . . . . . . Vacuum fluorescent display interface . . . . . . . VFD hardware . . . . . . . . . . . . . . . . . . . . . . . . VFD driver connection topologies . . . . . . . . . VFD driver device. . . . . . . . . . . . . . . . . . . . . . Static drive . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed drive . . . . . . . . . . . . . . . . . . . . . . Host request bit mapping to clocked output bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12.3.1 Static drive . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12.3.2 Multiplexed drive . . . . . . . . . . . . . . . . . . . . . . 8.12.4 Multiplex drive timing . . . . . . . . . . . . . . . . . . . 8.12.5 Multiplex drive pitfalls . . . . . . . . . . . . . . . . . . . 8.12.6 VFDData.req service configuration . . . . . . . . 8.12.7 VFDData.req service segment data . . . . . . . . 8.12.8 VFDData.cnf service . . . . . . . . . . . . . . . . . . . 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 10 Static characteristics . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 12 Application information . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information . . . . . . . . . . . . . . . . . . . . 19 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 23 23 23 24 25 25 25 26 26 26 27 27 27 28 29 30 30 31 31 32 33 34 35 36 37 37 38 38 38 38 38 38 39 40 40 41
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 August 2008 Document identifier: TDA9951_1

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